It is frequently desired to read and write data from dynamic random access memory (DRAM) integrated circuits (ICs). As the amount of data stored in each DRAM IC increases, there is need to be able to write data into, and read data out of, DRAMs with progressively higher bandwidth. This need requires new kinds of data input/output (I/O) systems and is not easily met.
Previous generations of DRAMs have included fast page mode DRAM and extended data output DRAM. These devices capture input data and drive output data at the falling edge of a column address strobe* (CAS*) signal, where the "*" indicates complement.
In synchronous DRAM (SDRAM), the data trigger point for read and write operations is the rising edge of the clock signal. These conventional DRAMs are referred to as single data rate (SDR) devices. The peak bandwidth (megabytes/second) of a memory system with such memories is given as: EQU (memory system bus width).times.(clock frequency) (Eq. 1)
Providing a higher peak bandwidth from a SDR DRAM system thus requires making the clock as fast as possible and expanding the system bus width to be as wide as possible.
However, the clock driver has to drive all DRAMs in the memory system in parallel. Accordingly, higher clock speeds may be difficult to achieve in practice. Additionally, because increasing the bus width also requires greater area on the board holding the DRAM system, it is not easy to increase the peak bandwidth of a SDR DRAM system by increasing bus width.
Double data rate (DDR) DRAM systems are a more attractive way to get a higher data rate and thus greater system bandwidth. In DDR systems, both the rising and falling edges of the clock signal or data strobe signal are trigger points for read and write operations. DDR DRAM systems thus provide double the peak data rate of comparable SDR DRAM systems for the same clock speed and bus width, but require increased timing accuracy.
In turn, new kinds of applications in which DRAMs are used for information storage and retrieval have been developed. These include applications involving PCs, servers, workstations, graphics processors and multimedia processors. As these kinds of applications have developed, needs for progressively larger amounts of data storage and retrieval, and therefore for more rapid data storage and retrieval, have also developed. In order to more rapidly access information stored in DRAMs, new kinds of interface architectures have been developed, including DDR I/O systems.
A differential clock (CLK and CLK*) scheme is used in DDR DRAM memory systems to address the increased timing accuracy requirements. However, there is still a need to synchronize internal clock signals with clocking signals in the circuitry external to the DDR DRAM. Further, because transitions in these clock signals at which data are transferred occur substantially more frequently than those of CAS* signals in SDR DRAMs, the timing tolerances are much tighter. As a result, there is need to maintain tighter timing tolerances in generating internal clocking signals CLK and CLK* that are synchronized with external clocking signals XCLK.
The clock speeds used in DDR DRAMs are increased relative to clock speeds for SDR DRAMs. One effect of the increased clock speed is to generate more heat in the DDR DRAM. In turn, timing of signals within the chip is modified by changes in the operating temperature of the DDR DRAM. When the timing of the signals within the DDR DRAM is shifted by too great an amount, errors occur in exchanging data between the DDR DRAM and circuitry external to the DDR DRAM.
Additionally, processing variations occurring during manufacturing of DRAMs can affect delays within a given DRAM. In turn, this may lead to situations where nominally identical DRAMs show different timing behavior and behavior variations over temperature. Moreover, some specific applications may require different temperature behavior than others.
Further, storage times for data stored in DRAM memory cells are a decreasing function of temperature, as is discussed in more detail in U.S. Pat. Nos. 5,278,796 and 5,276,843, which are assigned to the same assignee as the present invention and which are incorporated herein by reference. As the DRAM temperature increases, the time period during which data stored in memory cells in the DRAM are valid decreases. As a result, excessive temperatures can lead directly to loss of data stored in DRAMs.
What is needed is a capability for detecting the temperature of DRAMs that allows I/O operations to be slowed or suspended when the DRAM temperature exceeds a first threshold temperature and that allows I/O operations to speed up or resume when the temperature of the DRAM drops below a second threshold temperature. What is further needed is an ability to modify threshold temperatures and provide nonvolatile memory for storing modified threshold temperatures in DRAMs in response to measured performance criteria or specific application requirements.